As memory devices of all types have evolved, continuous strides have been made in improving their performance in a variety of respects. For example, the storage capacity of memory devices has continued to increase at geometric proportions. This increased capacity, coupled with the geometrically higher operating speeds of electronic systems containing memory devices, has made high memory device bandwidth ever more critical. One application in which memory devices, such as dynamic random access memory (“DRAM”) devices, require a higher bandwidth is their use as system memory in computer systems. As the operating speed of processors has increased, processors are able to read and write data at correspondingly higher speeds. Yet conventional DRAM devices often do not have the bandwidth to read and write data at these higher speeds, thereby slowing the performance of conventional computer systems. This problem is exacerbated by the trend toward multi-core processors and multiple processor computer systems. It is currently estimated that computer systems operating as high-end servers are idle as many as 3 out of every 4 clock cycles because of the limited data bandwidth of system memory devices. In fact, the limited bandwidth of DRAM devices operating as system memory can reduce the performance of computer systems to as low as 10% of the performance of which they would otherwise be capable.
Various attempts have been made to increase the data bandwidth of memory devices. For example, wider internal data buses have been used to transfer data to and from arrays with a higher bandwidth. However, doing so usually requires that write data be serialized and read data deserialized at the memory device interface. Another approach has been to simply scale up the size of memory devices or conversely shrink their feature sizes, but, for a variety of reasons, scaling has been incapable of keeping up with the geometric increase in the demand for higher data bandwidths.
More recently, proposals have also been made to stack several integrated circuit memory devices in the same package, but doing so threatens to create a large number of other problems to be overcome. These problems can be solved to a large extent by connecting the stack of interconnected memory devices to a logic die on which the memory devices are stacked. The logic die can then serve as a high-speed interface to the memory devices. However, taking advantage of the increased capabilities of this arrangement is more easily achieved if memory command and address signals are placed in a packet and coupled to the logic die through a high-speed bus. Yet many computer and other systems are designed to interface with memory devices using conventional memory command signals and conventional row and column address signals. Advanced memory systems formed by stacking memory devices on a logic die would therefore be unusable with such systems. However, memory device manufacturers generally desire to standardize their product offerings to the greatest extent possible to lessen the number of different memory devices that are manufactured, marketed, etc.
Therefore, a need exists for a method and system to allow advanced memory system formed by stacking interconnected memory device dice to be interfaced with systems by either using conventional memory commands and addresses or by using packets containing commands and addresses.